Chih-Chun Chang
Ph.D. Candidate
Department of Electrical and Computer Engineering
University of Wisconsin–Madison
GPU Performance • Heterogeneous Computing • ML Compilers • High-Performance Computing
chang292 _at_ wisc _dot_ edu
About
I am a fourth-year Ph.D. candidate in the Department of Electrical and Computer Engineering at the University of Wisconsin–Madison, advised by Prof. Tsung-Wei (TW) Huang. I also received my M.S. in Electrical and Computer Engineering from UW–Madison.
My research focuses on GPU performance optimization, heterogeneous computing, ML compilers, and high-performance computing. I develop efficient GPU software for large-scale graph analytics and statistical static timing analysis, with an emphasis on CUDA, Triton, memory-aware scheduling, and GPU kernel optimization.
Through multiple internships at Cadence Design Systems, I developed GPU-accelerated timing analysis algorithms for industrial-scale electronic design automation (EDA). My long-term interests include GPU systems, machine learning infrastructure, compiler technologies, and high-performance computing.
Research Highlights
SSTA-X
Industrial timing analysis
Accelerating statistical static timing analysis on GPUs for large-scale industrial EDA workloads.
GSAP
GPU graph analytics
GPU-accelerated stochastic graph partitioning for large-scale graph and timing-analysis workloads.
3× Cadence
Industry experience
Multiple internships focused on GPU acceleration, performance optimization, and timing analysis.
Selected Projects
GPU-Accelerated SSTA
GPU acceleration for statistical static timing analysis with memory-aware scheduling for industrial-scale timing workloads.
GSAP
A GPU-accelerated stochastic graph partitioner for large-scale graph analytics and timing-analysis workloads.
Selected Publications
Statistical Timing Graph Scheduling Algorithm for GPU Computation
[paper]
[project]
Chih-Chun Chang and Tsung-Wei Huang
ACM/IEEE Design Automation Conference Late-Breaking Result (DAC-LBR), San Francisco, CA, 2025
View all publications
SSTA-X: GPU-Accelerated First-Order Block-Based Statistical Static Timing Analysis
[paper]
Chih-Chun Chang, Yi-Hua Chung, Wan-Luan Lee, Boyang Zhang, and Tsung-Wei Huang
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems (TCAD), to appear, 2026
G-STAR: GPU-Accelerated Statistical Static Timing Analysis using Level-by-level Replication
[paper]
Boyang Zhang, Chih-Chun Chang, Yi-Hua Chung, Che Chang, Cheng-Hsiang Chiu, Aditya Das Sarma, and Tsung-Wei Huang
International European Conference on Parallel and Distributed Computing (Euro-Par), Pisa, Italy, 2026
iHyperG: Incremental Hypergraph Partitioning on GPU
[paper]
Wan-Luan Lee, Aditya Das Sarma, Che Chang, Chih-Chun Chang, and Tsung-Wei Huang
ACM/IEEE Design Automation Conference (DAC), Long Beach, CA, 2026
Optimizing CUDA Graph Scheduling with Reinforcement Learning: A Case Study in SSTA Propagation
[paper]
Cheng-Hsiang Chiu, Chedi Morchdi, Chih-Chun Chang, Cunxi Yu, Yi Zhou, and Tsung-Wei Huang
ACM/IEEE International Symposium on Machine Learning for CAD (MLCAD), Santa Cruz, CA, 2025
Statistical Timing Graph Scheduling Algorithm for GPU Computation
[paper]
[project]
[poster]
Chih-Chun Chang and Tsung-Wei Huang
ACM/IEEE Design Automation Conference Late-Breaking Result (DAC-LBR), San Francisco, CA, 2025
BQSim: GPU-accelerated Batch Quantum Circuit Simulation using Decision Diagram
[paper]
[project]
Shui Jiang, Yi-Hua Chung, Chih-Chun Chang, Tsung-Yi Ho, and Tsung-Wei Huang
ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Rotterdam, Netherlands, 2025
iTAP: An Incremental Task Graph Partitioner for Task-parallel Static Timing Analysis
[paper]
[project]
Boyang Zhang, Che Chang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yang Sui, Chih-Chun Chang, Yi-Hua Chung, Wan-Luan Lee, Zizheng Guo, Yibo Lin, and Tsung-Wei Huang
IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, 2025
GSAP: A GPU-Accelerated Stochastic Graph Partitioner
[paper]
[project]
Chih-Chun Chang, Boyang Zhang, and Tsung-Wei Huang
ACM International Conference on Parallel Processing (ICPP), Gotland, Sweden, 2024
G-PASTA: GPU-Accelerated Partitioning Algorithm for Static Timing Analysis
[paper]
Boyang Zhang, Dian-Lun Lin, Che Chang, Cheng-Hsiang Chiu, Bojue Wang, Wan Luan Lee, Chih-Chun Chang, Donghao Fang, and Tsung-Wei Huang
ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, 2024
uSAP: An Ultra-Fast Stochastic Graph Partitioner
[paper]
[project]
Chih-Chun Chang and Tsung-Wei Huang
IEEE High-performance and Extreme Computing Conference (HPEC), virtual, 2023
SoberMotion: Leveraging the Force of Probation Officers to Reduce the Risk of DUI Recidivism [Distinguished Paper Award]
[paper]
Chuang-Wen You, Ya-Fang Lin, Yaliang Chuang, Ya-Han Lee, Pei-Yi Hsu, Shih-Yao Lin, Chih-Chun Chang, Yi-Ju Chung, Yi-Ling Chen, Ming-Chyi Huang, Ping-Hsuan Shen, Hsin-Tung Tseng, and Hao-Chuan Wang
ACM International Joint Conference on Pervasive and Ubiquitous Computing (ACM UbiComp), Singapore, 2018
A Mobile Support System to Assist DUI Offenders on Probation in Reducing DUI Relapse
[paper]
Pei-Yi Hsu, Ya-Fang Lin, Jian-Lun Huang, Chih-Chun Chang, Shih-Yao Lin, Ya-Han Lee, Chuang-Wen You, Yaliang Chuang, Ming-Chyi Huang, Hsin-Tung Tseng, and Hao-Chuan Wang
ACM International Joint Conference on Pervasive and Ubiquitous Computing (ACM UbiComp), Hawaii, 2017
Industrial Experience
May 2026 – Aug. 2026
Graduate Intern
Cadence Design Systems, San Jose, CA, USA
GPU performance optimization for industrial-scale statistical static timing analysis.
May 2025 – Aug. 2025
Graduate Intern
Cadence Design Systems, San Jose, CA, USA
GPU acceleration of statistical timing analysis using CUDA and Triton.
May 2024 – Dec. 2024
Graduate Intern
Cadence Design Systems, San Jose, CA, USA
Memory-aware scheduling for GPU-accelerated statistical static timing analysis.
June 2017 – Aug. 2018
Research Assistant
NTU IoX Center, Taipei, Taiwan
Jan. 2019 – July 2019
Software Intern
HOPE English, Taipei, Taiwan
Education
Sep. 2023 – Present (Expected Spring 2027)
Ph.D. in Electrical and Computer Engineering
University of Wisconsin–Madison, Madison, WI, USA
Advisor: Prof. Tsung-Wei (TW) Huang
Aug. 2023 - Aug. 2025
M.S. in Electrical and Computer Engineering
University of Wisconsin–Madison, Madison, WI, USA
Aug. 2019 – May 2022
M.S. in Computer Science
National Tsing Hua University, Hsinchu, Taiwan
Aug. 2013 – May 2017
B.S. in Electrical Engineering
National Tsing Hua University, Hsinchu, Taiwan
Skills
GPU Programming
Parallel Computing
Compiler / Runtime
Domains
Awards
IEEE HPEC Innovation Award
uSAP: An Ultra-Fast Stochastic Graph Partitioner, 2023
ACM UbiComp Distinguished Paper Award
SoberMotion, 2018
NVIDIA Smart Embedded Robotics Challenge Champion
2016